1. Field of the Invention
This invention relates generally to built-in self-testing (BIST), and more particularly to a technique for testing phase lock loop (PLL) status during a Serializer/Deserializer (SERDES) internal loopback BIST.
2. Description of the Prior Art
Existing internal loopback built-in self-tests (BISTs) on a SerializerDeserializer (SERDES) are unable to verify the lock status of a PLL at the probe at the PLL operating frequency due to the speed limitations associated with the tester and the BIST architecture. Although the PLL lock status can be verified at final test by using external loopback test methodology, such verification is possible only if the customer design has the same number of transmitters and receivers on the same chip. In cases where a product has only a transmitter or receiver therefore, it becomes a serious test escape issue. Even for products having the same number of transmitters and receivers, it remains a test escape issue at the probe, resulting in assembly of faulty dies.
In view of the foregoing, it would be both beneficial and advantageous to provide a technique for allowing phase lock loop (PLL) status testing during SERDES internal loopback BIST.